This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to electrically testing integrated circuits.
As the size of integrated circuits shrinks, the number of devices within an integrated circuit has risen. For example, a rule of thumb common called Moore""s Law states that the number of transistors in a state of the art integrated circuit generally doubles every eighteen months. For many years this rule of thumb has generally been true. Thus, the increase in the number of cells within an integrated circuit has grown exponentially rather than linearly. Obviously, over the past several years the number of cells within a single integrated circuit has virtually exploded.
This tremendous and rapid increase in the number of active devices within an integrated circuit has come about as a result of innovation and changes in the way that the devices are designed and fabricated. Thus, many different issues have been overcome in accomplishing this increase in the capacity of integrated circuits. At the same time, however, this increase in the complexity and capacity of integrated circuits has created new challenges in regard to other aspects of integrated circuit fabrication, such as testing.
Integrated circuits typically receive a wide variety of testing throughout the fabrication process, both to ensure that the processes used to fabricate the integrated circuits are in control, and also to ensure that the structures formed by the various processes have the proper characteristics. Most of the tests performed during the fabrication process look at only an extremely narrow range of characteristics, which tend to be pertinent only to the step in the fabrication process that was most recently completed.
However, there are typically two different instances where a large battery of tests are performed on the integrated circuits, to ensure that the integrated circuit as a whole functions in the desired manner. The first of these comprehensive tests is performed at the end of front end processing, and is commonly called wafer sort. It is so called because the integrated circuits have been processed in wafer form up to this point in the fabrication process. The second of these tests is performed at the end of back end processing, and is commonly called final test. During back end processing the integrated circuits have been diced and packaged, and are then tested as completed devices.
Because integrated circuits have so many more active devices than in times past, the time required for wafer sort and final test, jointly and severally referred to as comprehensive testing herein, has likewise increased exponentially. Because this required length of time adds an unacceptable labor and equipment expense to the fabrication costs of the integrated circuits, there is continual pressure to discover and implement alternate procedures for testing the integrated circuits, which procedures are preferably less time consuming but at least adequately thorough.
Also, traditionally, most tests are performed as a pass/fail (or Boolean) test to set limits in the test program. There is a growing need for tests that measure the actual working range of the integrated circuit so that it can be determined if the integrated circuit is significantly different or an outlier to the intrinsic (defect free) population of all integrated circuits in the fabrication lot. This method of testing Is also becoming important to help identify circuits that contain subtle defects that do not fail the Boolean tests, but are likely to fail over time or in the customer application at temperature or at high speeds. Unfortunately, due to the growing gate count of integrated circuits and the growing cost of the test equipment, these types of tests can be cost prohibitive due to the test time required.
What is needed, therefore, is a test methodology by which an integrated circuit can be adequately tested within an amount of time that is less than that of prior art techniques.
The above and other needs are met by a method of testing an integrated circuit. A first subset of test parameters, which may include vectors, is selected from a full set of test parameters designed to characterize given properties of the integrated circuit. A first subset of devices in the integrated circuit is tested with the first subset of test parameters, using different input levels to determine an acceptable low input level and an acceptable high input level for the first subset of test parameters on the first subset of devices. At least a second subset of devices in the integrated circuit is tested, where the second subset of devices is greater in number than the first subset of devices. The test is accomplished with at least a second subset of test parameters using the acceptable low input level and the acceptable high input level, to determine whether the integrated circuit functions properly at the acceptable low input level and the acceptable high input level. The integrated circuit is selectively binned based upon the determination of whether the integrated circuit functions properly at the acceptable low input level and the acceptable high input level.
In this manner, a first, qualifying test is performed on a limited number of devices within the integrated circuit, and with a limited number of test parameters. When the acceptable low and high input levels from this qualifying test are determined, a second more complete test is performed on the integrated circuit, to determine whether the integrated circuit functions properly at the acceptable low and high input levels from the qualifying test. Thus, a complete test to find the acceptable low and high input levels of every device or device group on the integrated circuit does not need to be completed for every test parameter. In this way, a great deal of time is saved during the testing process.
In a most preferred embodiment of the invention, the integrated circuit is tested for minimum VDD and maximum VDD by first selecting a first subset of test vectors from a full set of test vectors designed to characterize minimum VDD and maximum VDD of the integrated circuit. A first subset of devices in the integrated circuit is tested with the first subset of test vectors using different input voltage levels to determine a minimum VDD and a maximum VDD for the first subset of test vectors on the first subset of devices. A new minimum VDD is calculated by adding a first guard band value from the minimum VDD, and a new maximum VDD is calculated by subtracting a second guard band value to the maximum VDD. At least a second subset of devices in the integrated circuit is then tested, where the second subset of devices is greater in number than the first subset of devices, with at least a second subset of test vectors using the minimum VDD and the maximum VDD, to determine whether the integrated circuit functions properly at the minimum VDD and the maximum VDD. The integrated circuit is selectively binned based upon the determination of whether the integrated circuit functions properly at the minimum VDD and the maximum VDD.
In other preferred embodiments, a binary search of different input voltage levels is used to test the first subset of devices in the integrated circuit with the first subset of test vectors. The method is preferably accomplished at a maximum speed of the integrated circuit, but may alternately be accomplished at a nominal speed of the integrated circuit. The integrated circuit is preferably selectively binned by either scrapping or downgrading the integrated circuit based upon the determination of whether the integrated circuit functions properly at the minimum VDD and the maximum VDD.